The present invention relates to a method and/or architecture for an AND plane of a programmable logic device generally and, more particularly, to a method and/or architecture for a degenerate network for an AND plane of a programmable logic device.
Referring to FIG. 1, a schematic diagram of a circuit 10 illustrating an implementation of an AND plane is shown. The circuit 10 illustrates a row of a 39-input AND plane. The circuit 10 provides for each of the 39 inputs (e.g., IT0-IT38) and a digital complement of each of 39 inputs (e.g., ITB0-ITB38) to be wire NORed. Seventy-eight configuration bits M control which of the inputs IT0-IT38 and complements ITB0-ITB38 are NORed. A sense amplifier 12 generates a row output in response to the wired NOR result.
Disadvantages of the sense amplifier 12 based AND plane include (i) sensitivity to the switching of a number of pull down paths, (ii) susceptibility to glitching, and (iii) continuous DC power consumption.
The present invention concerns a programmable logic device comprising one or more first stages and one or more second stages. The one or more first stages may comprise one or more gates of a first type each having a first number of inputs. The one or more second stages may comprise one or more gates of a second type each having a second number of inputs, wherein said first and second stages are interlaced.
The objects, features and advantages of the present invention include providing a method and/or architecture for a degenerate network for an AND plane of a programmable logic device that may (i) provide minimal skew, (ii) use symmetric gates, (iii) use a particular type of gate for each stage, (iv) connect un-used inputs to a voltage or ground supply, (v) provide minimal propagation delay, (vi) provide zero DC power consumption, (vii) provide glitch free operation and/or (v) provide a fully CMOS, degenerate N-input AND plane.